Trench MOSFET device with improved on-resistance

ABSTRACT

A trench MOSFET device and method of making the same. The trench MOSFET device comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of the first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial region from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a doped region of the first conductivity type formed within the epitaxial layer between a bottom portion of the trench and the substrate, wherein the doped region has a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer; (g) a body region of a second conductivity type formed within an upper portion of the epitaxial layer and adjacent the trench, wherein the body region extends to a lesser depth from the upper surface of the epitaxial layer than does the trench; and (h) a source region of the first conductivity type formed within an upper portion of the body region and adjacent the trench. The presence of the doped region lying between the bottom portion of the trench and the substrate (also referred to herein as a “trench bottom implant”) serves to reduce the on-resistance of the device.

BACKGROUND OF THE INVENTION

[0001] The present invention relates to trench MOSFET devices, and moreparticularly to trench MOSFET devices with improved on-resistance.

[0002] A trench MOSFET (metal-oxide-semiconductor field-effecttransistor) is a transistor in which the channel is formed verticallyand the gate is formed in a trench extending between the source anddrain. The trench, which is lined with a thin insulator layer such as anoxide layer and filled with a conductor such as polysilicon (i.e.,polycrystalline silicon), allows less constricted current flow andthereby provides lower values of specific on-resistance. Examples oftrench MOSFET transistors are disclosed, for example, in U.S. Pat. Nos.5,072,266, 5,541,425, and 5,866,931, the disclosures of which are herebyincorporated by reference.

[0003] As a specific example, FIG. 1 illustrates half of a hexagonallyshaped trench MOSFET structure 21 disclosed in U.S. Pat. No. 5,072,266.The structure includes an n+ substrate 23, upon which is grown a lightlydoped n epitaxial layer 25 of a predetermined depth d_(epi). Within theepitaxial layer 25, p body region 27 (p, p+) is provided. In the designshown, the p body region 27 is substantially planar (except in a centralregion) and typically lays a distance d_(min) below the top surface ofthe epitaxial layer. Another layer 28 (n+) overlying most of the p bodyregion 27 serves as source for the device. A series of hexagonallyshaped trenches 29 are provided in the epitaxial layer, opening towardthe top and having a predetermined depth d_(tr). The trenches 29 aretypically lined with oxide and filled with conductive polysilicon,forming the gate for the MOSFET device. The trenches 29 define cellregions 31 that are also hexagonally shaped in horizontal cross-section.Within the cell region 31, the p body region 27 rises to the top surfaceof the epitaxial layer and forms an exposed pattern 33 in a horizontalcross section at the top surface of the cell region 31. In the specificdesign illustrated, the p+ central portion of the p body region 27extends to a depth d_(max) below the surface of the epitaxial layer thatis greater than the trench depth d_(tr) for the transistor cell so thatbreakdown voltage is away from the trench surface and into the bulk ofthe semiconductor material.

[0004] A typical MOSFET device includes numerous individual MOSFET cellsthat are fabricated in parallel within a single chip (i.e., a section ofa semiconductor wafer). Hence, the chip shown in FIG. 1 containsnumerous hexagonal-shaped cells 31 (portions of five of these cells areillustrated). Cell configurations other than hexagonal configurationsare commonly used, including square-shaped configurations. In a designlike that shown in FIG. 1, the substrate region 23 acts as a commondrain contact for all of the individual MOSFET cells 31. Although notillustrated, all the sources for the MOSFET cells 31 are typicallyshorted together via a metal source contact that is disposed on top ofthe n+ source regions 28. An insulating region, such asborophosphosilicate glass (not shown) is typically placed between thepolysilicon in the trenches 29 and the metal source contact to preventthe gate regions from being shorted with the source regions.Consequently, to make gate contact, the polysilicon within the trenches29 is typically extended into a termination region beyond the MOSFETcells 31, where a metal gate contact is provided on the polysilicon.Since the polysilicon gate regions are interconnected with one anothervia the trenches, this arrangement provides a single gate contact forall the gate regions of the device. As a result of this scheme, eventhough the chip contains a matrix of individual transistor cells 31,these cells 31 behave as a single large transistor.

[0005] Demand persists for trench MOSFET devices having ever-loweron-resistance. One way to decrease on-resistance is to decrease thethickness of the epitaxial layer. As a result, the region of theepitaxial layer lying between the body region and the substrate (seenumeral 25 in FIG. 1) is reduced in thickness. Since this region is ofrelatively high resistivity, the on-resistance of the device is reduced.However, as is known in the art, the risk of breakdown increases as theepitaxial layer becomes thinner, particularly in the termination region,which is more vulnerable to breakdown.

SUMMARY OF THE INVENTION

[0006] According to an embodiment of the invention, a trench MOSFETdevice is provided. The device comprises: (a) a substrate of a firstconductivity type (preferably an n-type conductivity silicon substrate);(b) an epitaxial layer of the first conductivity type over thesubstrate, wherein the epitaxial layer has a lower majority carrierconcentration than the substrate; (c) a trench extending into theepitaxial region from an upper surface of the epitaxial layer; (d) aninsulating layer (preferably an oxide layer) lining at least a portionof the trench; (e) a conductive region (preferably a doped polysiliconregion) within the trench adjacent the insulating layer; (f) a dopedregion of the first conductivity type formed within the epitaxial layerbetween a bottom portion of the trench and the substrate, wherein thedoped region has a majority carrier concentration that is lower thanthat of the substrate and higher than that of the epitaxial layer; (g) abody region of a second conductivity type (preferably p-typeconductivity) formed within an upper portion of the epitaxial layer andadjacent the trench, wherein the body region extends to a lesser depthfrom the upper surface of the epitaxial layer than does the trench; and(h) a source region of the first conductivity type formed within anupper portion of the body region and adjacent the trench.

[0007] The presence of the doped region lying between the bottom portionof the trench and the substrate (sometimes referred to herein as a“trench bottom implant” based on its preferred mode of formation) servesto reduce the on-resistance of the device. Preferably this regionextends more than 50% of the distance from the trench bottom to thesubstrate, more preferably 100% of the distance from the trench bottomto the substrate.

[0008] According to another embodiment of the invention, a method offorming a trench MOSFET device is provided. The method comprises: (a)providing a substrate of a first conductivity type; (b) depositing anepitaxial layer of the first conductivity type over the substrate, theepitaxial layer having a lower majority carrier concentration than thesubstrate; (c) forming a body region of a second conductivity typewithin an upper portion of the epitaxial layer; (d) etching a trenchextending into the epitaxial region from an upper surface of theepitaxial layer such that the trench extends to a greater depth from theupper surface of the epitaxial layer than does the body region; (e)forming a doped region of the first conductivity type between a bottomportion of the trench and the substrate such that the doped region has amajority carrier concentration that is lower than that of the substrateand higher than that of the epitaxial layer; (f) forming an insulatinglayer lining at least a portion of the trench; (g) forming a conductiveregion within the trench adjacent the insulating layer; (h) forming asource region of the first conductivity type within an upper portion ofthe body region and adjacent the trench.

[0009] The doped region is preferably formed by a method comprisingimplanting a dopant of the first conductivity type into the epitaxialregion, and diffusing dopant of the first conductivity type at elevatedtemperature. More preferably, the doped region is formed in connectionwith the trench by a method comprising: (a) forming a trench mask on theepitaxial layer; (b) etching the trench through the trench mask; (c)implanting a dopant of the first conductivity type through the trenchmask; and (c) diffusing the dopant at elevated temperature. Even morepreferably, the diffusion step is conducted concurrently with the growthof a sacrificial oxide along walls of the trench.

[0010] Trench bottom implants have been previously used to address aproblem arising from devices that have deep body regions which extend togreater depths than the trenches (such as the deep body regions of FIG.1). More specifically, U.S. Pat. No. 5,929,481 is directed to a trenchMOSFET device having deep body regions that extend deeper than thetrench. Unfortunately, these deep body regions, which are provided toavoid trench corner electrical breakdown, create the problem of aparasitic JFET at the trench bottom. To reduce this parasitic JFET, adoped trench bottom implant region is provided at the bottom of thetrench, which extends into the surrounding drift region. The trenchbottom implant region has the same doping type, but is more highlydoped, than the surrounding drift region. In contrast to U.S. Pat. No.5,929,481, however, the trench MOSFET devices of the present inventionare not provided with such deep body regions. Instead, the trenches ofthe devices of the present invention extend to a greater depth than dothe body regions.

[0011] One advantage of the present invention is that a trench MOSFETcell is provided which has improved on-resistance.

[0012] Another advantage of the present invention is that a trenchMOSFET cell with improved on-resistance is provided, without asubstantial increase in design and process complexity.

[0013] Another advantage of the present invention is that a trenchMOSFET cell can be provided, which has reduced resistance in theepitaxial layer between the trench bottoms and the substrate. In thisway, on-resistance is reduced without thinning the epitaxial layer andcompromising breakdown characteristics within the termination region.

[0014] The above and other embodiments and advantages of the presentinvention will become immediately apparent to those of ordinary skill inthe art upon review of the Detailed Description and Claims to follow.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015]FIG. 1 is a schematic cross-sectional view of a trench MOSFETdevice in the prior art.

[0016]FIG. 2 is a schematic cross-sectional view of a trench MOSFETdevice, according to an embodiment of the present invention.

[0017]FIG. 3 shows approximate plots of concentration v. distance (inarbitrary units and scale) over portions of the cross-sections definedby lines A-A′ (curve a) and B-B′ (curve b) of FIG. 2.

[0018]FIGS. 4A through 4C are schematic cross-sectional viewsillustrating a method of making a trench MOSFET device like of FIG. 2,according to an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION

[0019] The present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichpreferred embodiments of the present invention are shown. This inventionmay, however, be embodied in different forms and should not be construedas limited to the embodiments set forth herein.

[0020] The present invention is directed to novel trench MOSFETstructures in which a region of relatively high majority carrierconcentration (sometimes referred to herein as a “trench bottom implant”based on its preferred mode of formation) is provided between the trenchbottom and the substrate. One advantage associated with such a trenchMOSFET structure is improved on-resistance.

[0021]FIG. 2 illustrates a trench MOSFET in accordance with anembodiment of the present invention. In the trench MOSFET shown, anepitaxial layer 201 is provided on an N+ substrate 200.

[0022] The N+ substrate 200 in this specific example is a siliconsubstrate having a thickness ranging, for example, from 10 to 25 milsand a net doping concentration ranging, for example, from 1×10¹⁹ to1×10²⁰ cm⁻³.

[0023] N− regions 202 are found in the lower portion of the epitaxiallayer 201. In this example, these regions have a thickness ranging from,for example, 2 to 5 microns and a net doping concentration ranging, forexample, from 4×10¹⁵ to 8×10¹⁶ cm⁻³.

[0024] P-body regions 204 are found in the upper portion of theepitaxial layer 201. In the example shown, these P-body regions 204range, for example, from 1 to 2 microns in thickness and have a netdoping concentration ranging, for example, from 1×10¹⁷ to 1×10¹⁸ cm⁻³.

[0025] Trenches formed within the epitaxial layer are lined with aninsulator 210, such as oxide, and are filled with a conductor 211, suchas doped polysilicon, providing the gate electrode function of thedevice. The trenches typically have a depth of 1.5 to 2.5 microns. Wheresilicon oxide (typically as silicon dioxide) is used as the insulator210, it can be for example, 500 to 700 Angstroms thick. Wherepolysilicon is used as the conductor 211, it can have a resistivity of,for example, 1 to 15 ohm/sq. The regions between the trenches arefrequently referred to as “mesas” or “trench mesas”, based on theirshapes. These regions are commonly square or hexagonal in plan view.

[0026] In accordance with the present invention, N regions 206 (alsoreferred to herein as “trench bottom implants”) are provided between thetrench bottoms and the N+ substrate. N regions 206 have a net dopingconcentration ranging, for example, from 1×10¹⁸ to 5×10¹⁹ cm⁻³. Theseregions 206 preferably extend the entire distance from the trenchbottoms to the N+ substrate 200 as shown, but can also partially bridgethe distance if desired. Typically, these regions range from 1 to 6microns in depth.

[0027] The trench MOSFET device of FIG. 2 also contains N+ sourceregions 212, which extend, in the embodiment illustrated, to a depth of0.3 to 0.5 micron from the epitaxial layer surface and have net dopingconcentrations ranging, for example, from 5×10¹⁹ to 5×10²⁰ cm⁻³.

[0028] Electrical contact is made with the N+ source regions 212 viametal source contact 218. Insulating regions such as BPSG(borophosphosilicate glass) regions 216 prevent the polysilicon regions211 associated with the gate electrodes from being shorted to the N+source regions 212 through the source contact 218. A separate metal gatecontact (not shown) is typically connected to the gate runner portion ofthe polysilicon 211 located outside of the region of the trench MOSFETcells. A metal drain contact (not shown) is also typically providedadjacent the N+ substrate 200.

[0029] Illustrated in curve a of FIG. 3 is the approximate dopingprofile found along the portion of line A-A′ of FIG. 2 that begins atthe trench bottom and extends into the substrate 200. The left-handportion of curve a corresponds to N region 206, while the right-handportion corresponds to the N+ substrate 200. For comparison, theapproximate doping profile found along a parallel portion of line B-B′within FIG. 2 is illustrated in curve b of FIG. 3. The left-hand portionof curve b corresponds to the N− epitaxial region 202, while theright-hand portion corresponds to the N+ substrate 200.

[0030] Although not wishing to be bound by theory, it is believed that,upon creation of a potential difference between the p-body regions 204and the polysilicon regions 211 of the gate, charges are capacitivelyinduced within the p-body body regions 204 adjacent to the gate oxidelayer 210, resulting in the formation of channels within the p-bodyregions 204. When another potential difference is provided between thesources 212 and the N+ substrate 200 (corresponding to the drain), acurrent flows from the sources 212 to the N+ substrate 200 through thechannels formed in the P-body regions 204 adjacent the gate oxide layer210, and the trench MOSFET is said to be in the power-on state. It isfurther believed that the device of FIG. 2 has improved on-resistance,because the N regions 206 formed at the bases of the trenches providepaths of reduced resistance for the current flowing from the sources 212to the drain (N+ substrate 200) while the transistor is in the power-onstate.

[0031] A method for manufacturing a trench MOSFET like that shown inFIG. 2 will now be described in connection with FIGS. 4A to FIG. 4C, inaccordance with one embodiment of the present invention.

[0032] Turning now to FIG. 4A, an N doped epitaxial layer 201 isinitially grown on an N+ doped substrate 200. The N+ doped substrate200, for example, can be from 10 to 25 mils and have a net dopingconcentration ranging, for example, from 1×10¹⁹ to 1×10²⁰ cm⁻³. Theepitaxial layer 201, for example, can have a net n-type dopingconcentration of 4×10¹⁵ to 8×10¹⁶ cm⁻³ and can range from 3 to 10microns in thickness.

[0033] Using masking as appropriate, a P-type region 204 is then formedin the epitaxial layer 201 by implantation and diffusion. For example,the epitaxial layer 201 may be implanted with boron followed bydiffusion at elevated temperature to produce a P-type region 204, whichcan be 1 to 2 microns thick and have a net p-type doping concentrationranging, for example, from 1×10¹⁷ to 1×10¹⁸ cm⁻³. After this step, anN-portion 202 of the epitaxial layer 201 remains, which can be 2 to 5microns thick. N-portion 202 has the n-type doping concentration notedabove for epitaxial layer 201.

[0034] A mask oxide layer 203 is then deposited, for example, bychemical vapor deposition, and etched by reactive ion etch after beingprovided with a patterned trench mask (not shown). The resultingstructure is shown in FIG. 4A.

[0035] Trenches are then etched through apertures in the patterned maskoxide layer 203, typically by reactive ion etching. Trench depths inthis example are about 1.5 to 2.5 microns. Discrete P-body regions 204are established as a result of this trench-forming step.

[0036] At this point, an n-type dopant, preferably phosphorous, isimplanted into the structure using the trench mask as an implantationmask. In this example, phosphorous is implanted at 80 to 100 keV with adosage of 5×10¹⁵ to 1×10¹⁷ cm⁻³. The resulting structure is shown inFIG. 4B. The dashed lines found below the trench bottom illustrate thepresence of phosphorous within the structure.

[0037] Although the implanted n-type dopant (e.g., phosphorous) can bediffused into the structure at this point by simply heating thestructure, according to a preferred embodiment, dopant diffusion iscarried out concurrently with the formation of a sacrificial oxidelayer. Specifically, a sacrificial oxide layer is grown within thetrench at this point, typically by dry oxidation at 900 to 1150° C. for20 to 60 minutes. As a result, in addition to forming sacrificial oxideregions 205, this elevated temperature step drives the implanted n-typedopant into the N-type region 202 of the epitaxial layer, forming Nregions 206. The resulting structure is illustrated in FIG. 4C.

[0038] Subsequently, the trench MOSFET is completed to form a structurelike that shown in FIG. 2. For example, the sacrificial oxide regions205 seen in FIG. 4C are removed from the trenches, preferably by wetetch. An oxide layer, which is preferably 500 to 700 Angstroms thick, isthen grown over the trench bottom, for example, by dry oxidation at 900to 1100° C. for 20 to 60 minutes. Portions of this oxide layerultimately form the gate oxide regions 210 for the finished device.

[0039] The surface of the structure is then covered, and the trenchesare filled, with a polysilicon layer, preferably using CVD. Thepolysilicon is typically doped N-type to reduce its resistivity. N-typedoping can be carried out, for example, during CVD with phosphorouschloride or by implantation with arsenic or phosphorous. The polysiliconlayer is then etched, for example, by reactive ion etching. Thepolysilicon layer within the trench segments is commonly slightlyover-etched due to etching uniformity concerns, and the thus-formedpolysilicon gate regions 211 typically have top surfaces that are 0.1 to0.2 microns below the adjacent surface of the epitaxial layer 204.

[0040] A patterned masking layer is then provided and n+ source regions212, which preferably extend to a depth of 0.3 to 0.5 microns and fromthe epitaxial layer surface and have net doping concentrations ranging,for example, from 5×10¹⁹ to 5×10²⁰ cm⁻³, are formed in upper portions ofthe epitaxial layer through the masking layer via an implantation anddiffusion process. Implantation is preferably conducted through animplant oxide to avoid implant-channeling effects, implant damage, andheavy metal contamination during formation of the source regions.

[0041] A BPSG (borophosphosilicate glass) layer is then formed over theentire structure, for example, by PECVD. After providing the structurewith a patterned photoresist layer, the structure is then etched,typically by reactive ion etching, to remove the BPSG and oxide layersover selected portions of the structure, forming BPSG regions 216. Thepatterned photoresist layer is then removed, and a metal contact layeris deposited, forming source contact 218. Gate and drain contacts (notshown) are also typically provided. The resulting structure is like thatof FIG. 2.

[0042] Although various embodiments are specifically illustrated anddescribed herein, it will be appreciated that modifications andvariations of the present invention are covered by the above teachingsand are within the purview of the appended claims without departing fromthe spirit and intended scope of the invention. As one example, themethod of the present invention may be used to form a structure in whichthe conductivities of the various semiconductor regions are reversedfrom those described herein.

1. A trench MOSFET device comprising: a substrate of a firstconductivity type; an epitaxial layer of said first conductivity typeover said substrate, said epitaxial layer having a lower majoritycarrier concentration than said substrate; a trench extending into saidepitaxial region from an upper surface of said epitaxial layer; aninsulating layer lining at least a portion of said trench; a conductiveregion within said trench adjacent said insulating layer; a doped regionof said first conductivity type formed within said epitaxial layerbetween a bottom portion of said trench and said substrate, said dopedregion having a majority carrier concentration that is lower than thatof said substrate and higher than that of said epitaxial layer; a bodyregion of a second conductivity type formed within an upper portion ofsaid epitaxial layer and adjacent said trench, said body regionextending to a lesser depth from said upper surface of said epitaxiallayer than does said trench; and a source region of said firstconductivity type formed within an upper portion of said body region andadjacent said trench.
 2. The trench MOSFET device of claim 1, whereinsaid doped region extends more than 50% of the distance from said trenchbottom to said substrate.
 3. The trench MOSFET device of claim 2,wherein said doped region spans 100% of the distance from said trenchbottom to said substrate.
 4. The trench MOSFET device of claim 1,wherein said first conductivity type is n-type conductivity and saidsecond conductivity type is p-type conductivity.
 5. The trench MOSFETdevice of claim 4, wherein said doped region is doped with phosphorous.6. The trench MOSFET device of claim 4, wherein said substrate is an N+substrate, said epitaxial layer is an N− epitaxial layer, said dopedregion is an N region, said body region is a P region, said sourceregion is an N+ region, and.
 7. The trench MOSFET device of claim 1,wherein said trench MOSFET device is a silicon device.
 8. The trenchMOSFET device of claim 7, wherein said first insulating layer is asilicon oxide layer.
 9. The trench MOSFET device of claim 7, wherein theconductive region is a doped polycrystalline silicon region.
 10. Thetrench MOSFET device of claim 1, wherein the doped region ranges from 1to 6 microns in thickness.
 11. The trench MOSFET device of claim 4,wherein the doped region has a net n-type carrier concentration rangingfrom 1×10¹⁸ to 5×10¹⁹ cm⁻³.
 12. The trench MOSFET device of claim 1,wherein said trenches define a plurality of square-shaped orhexagonal-shaped MOSFET cells.
 13. A trench MOSFET device comprising: asilicon substrate of n-type conductivity; a silicon epitaxial layer ofn-type conductivity over said substrate, said epitaxial layer having alower majority carrier concentration than said substrate; a trenchextending into said epitaxial region from an upper surface of saidepitaxial layer; a silicon oxide insulating layer lining at least aportion of said trench; a doped polycrystalline silicon region withinsaid trench adjacent said silicon oxide layer; a doped region of n-typeconductivity provided between a bottom portion of said trench and saidsubstrate, said doped region having a majority carrier concentrationthat is lower than that of said substrate and higher than that of saidepitaxial layer; a body region of p-type conductivity formed within anupper portion of said epitaxial layer and adjacent said trench, saidbody region extending to a lesser depth from said upper surface of saidepitaxial layer than does said trench; and a source region of n-typeconductivity formed within an upper portion of said body region andadjacent said trench.
 14. The trench MOSFET device of claim 13, whereinsaid doped region spans 100% of the distance from said trench bottom tosaid substrate.
 15. The trench MOSFET device of claim 13, wherein saiddoped region is doped with phosphorous.
 16. The trench MOSFET device ofclaim 13, wherein the doped region ranges from 1 to 6 microns inthickness.
 17. The trench MOSFET device of claim 13, wherein the dopedregion has a net n-type carrier concentration ranging from 1×10¹⁸ to5×10¹⁹ cm⁻³.
 18. A method of forming a trench MOSFET device comprising:providing a substrate of a first conductivity type; depositing anepitaxial layer of said first conductivity type over said substrate,said epitaxial layer having a lower majority carrier concentration thansaid substrate; forming a body region of a second conductivity typewithin an upper portion of said epitaxial layer; etching a trenchextending into said epitaxial region from an upper surface of saidepitaxial layer, said trench extending to a greater depth from saidupper surface of said epitaxial layer than does said body region;forming a doped region of said first conductivity type between a bottomportion of said trench and said substrate, said doped region having amajority carrier concentration that is lower than that of said substrateand higher than that of said epitaxial layer; forming an insulatinglayer lining at least a portion of said trench; forming a conductiveregion within said trench adjacent said insulating layer; and forming asource region of said first conductivity type within an upper portion ofsaid body region and adjacent said trench.
 19. The method of claim 18,wherein said step of forming said doped region comprises: (a) implantinga dopant of said first conductivity type into said epitaxial region; and(b) diffusing dopant of said first conductivity type at elevatedtemperature.
 20. The method of claim 19, wherein said dopant is diffuseduntil the doped region spans more than 50% of the distance from saidtrench bottom to said substrate.
 21. The method of claim 19, whereinsaid dopant is diffused until the doped region spans 100% of thedistance from said trench bottom to said substrate.
 22. The method ofclaim 19, wherein said first conductivity type is n-type conductivityand said second conductivity type is p-type conductivity.
 23. The methodof claim 22, wherein said dopant is phosphorous.
 24. The method of claim18, wherein said steps of forming said trenches and forming said dopedregion comprise: (a) forming a trench mask on said epitaxial layer; (b)etching said trench through said trench mask; (c) implanting a dopant ofsaid first conductivity type through said trench mask; and (c) diffusingsaid dopant of said first conductivity type at elevated temperature. 25.The method of claim 24, wherein said elevated temperature is provided bya step in which a sacrificial oxide is grown along walls of said trench.26. The method of claim 18, wherein said trench MOSFET device is asilicon device.
 27. The method of claim 18, further comprising: forminga metallic drain contact adjacent said semiconductor substrate, forminga metallic source contact adjacent an upper surface of said sourceregion, and forming a metallic gate contact adjacent an upper surface ofsaid conductive region remote from said source region.